The present invention relates to a process for manufacturing calibration structures particularly for the calibration of machines for measuring alignment in integrated circuits in general.
In the manufacture of integrated circuits by means of photolithographic processes and the like, a technical problem which occurs with increasing frequency is related to the calibration of the measurement machines which are intended to measure the alignment of the different layers of the integrated circuit, i.e., to check the possible misalignment of successive masks on a same substrate made, for example, of silicon, gallium arsenide and the like.
The precision required of these measurement machines are increasingly high; this fact is related to the increasingly higher density and circuit complexity of the various integrated circuits. Indeed, for example, for erasable and programmable read-only memories, technically known as EPROMs, having a complexity equal to 1 megabit, the alignment tolerances must be smaller than 0.40 micrometers; for a complexity equal to 4 megabits, the alignment tolerances must be smaller than 0.25 micrometers; for EPROMs having a complexity equal to 64 megabits, the alignment tolerances must be smaller than 0.10 micrometers with measurement accuracies of less than 15-20 nanometers, i.e., equal at most to one-fifth of the maximum alignment tolerance.
In order to achieve the above mentioned alignment levels, it is indispensable to provide systems for the calibration of the measurement machines which are accurate and precise to be able to check the operation of photolithographic machines, known as wafer steppers, such calibrated measurement machines indicate any corrections to be performed in order to eliminate errors, such as magnification factors of the lens systems, alignment offsets, combined rotations and translations and the like, as well as the errors in the product, i.e., the silicon substrates or wafers, after the various masking steps.
For some particular applications, it is already possible to have calibration patterns on a single mask with a known misalignment, by means of which it is possible to calibrate the measurement machines. The limitation of these methods is due to the fact that all calibration or reference patterns are currently etched in the same layer, whereas it is indispensable, in manufacturing practice, to evaluate the misalignment among different layers.